1. Field of the Invention
This invention relates to analog-to-digital converters (ADCs), and more particularly to ADCs that incorporate a predictive function by which a predicted input signal value is compared with the actual input signal to generate an error signal, and the error signal is combined with the predicted value to produce an output.
2. Description of the Related Art
ADCs convert analog quantities such as a voltage or a current into digital words. Numerous different types of ADC designs have been implemented; a general treatment of the subject is provided in Grebene, Bipolar and MOS Analog Integrated Circuit Design. John Wiley & Sons, chapter 15, pages 825-879 (1984). The two most pertinent designs for purposes of the present invention are a multi-pass subranging converter using one or a pair of sample-and-hold circuits, and the differential pulse code modulation (DPCM) linear predictive coder.
A multi-pass ADC using a sample-and-hold circuit is described in Harris, "A Wide Dynamic Range A-to-D Converter Using a Band Limited Predictor-Corrector DPCM Algorithm", IEEE Int'l Conf. on Comm., Jun. 8-10, 1987, and a similar circuit is illustrated in FIG. 1 herein. An input analog signal is fed into a sample-and-hold circuit 2 that obtains periodic analog samples of the input signal. Each sample is provided to a quantizer Q1 that provides a course digitized version of the sample to both a digital-to-analog converter (DAC) 4 and an output summing junction 6. The DAC 4 converts the sample back to analog format and delivers it to another summing junction 8.
The input signal sample from sample-and-hold circuit is also transmitted to the summing junction 8, preferably via a second sample-and-hold circuit 10. This second sample-and-hold allows the system to be speeded up with the use of a biphase clock for both sample-and-holds, but in general is not essential. The DAC output is subtracted from the sampled input circuit at summing junction 8 to yield a signal that represents the combined conversion errors of quantizer Q1 and DAC 4 (the DAC is generally assumed to have a zero error). This error signal is then expanded by a factor of A in an amplifier A1 to bring it up to the full scale of a second quantizer Q2, which is typically about 1-2 volts peak-to-peak. After quantization by Q2, the amplified digital error signal is scaled down by a factor of A in a digital divider 12 to yield a true-scale digital error signal. The output summing junction 6 combines the coarsely digitized input sample from Q1 with the signal from digital divider A that represents the error associated with the course signal from Q1, so that the resultant output digital signal on output line 14 is a more accurate representation of the input analog signal and would be obtained by simply quantizing the input.
While the circuit of FIG. 1 provides good conversion accuracy, it requires an extreme linearity in the sample-and-hold circuits and in the DAC, and an intricate timing sequence to ensure that the input signals to the summing junction 6 and 8 represent the same sample. The switching nature of the sample-and-hold circuits also places a severe restriction upon the input signal's amplitude and frequency, which is necessary to avoid the introduction of unacceptable distortion components. Video band two-pass ADCs of this design typically require two sample-and-hold circuits.
A feedback DPCM ADC that utilizes a predictor function to provide extended dynamic range to a conventional ADC is illustrated in FIG. 2. The circuit can conveniently be described beginning at the output line 16, which carries the circuit's digital output signal. The output signal is updated periodically at the ADC function's sampling frequency, and each output is also fed into a predictor circuit 18 that predicts the value of the next periodic input signal based upon the values of the most recent output signal samples. The predicted signal value, in digital format, is supplied to an output summing junction 20 and also to a DAC 22. The output of the DAC, which represents the predicted value of the next signal in analog format, is compared with the actual input analog signal in a summing junction 24, with the predicted value subtracted from the actual value to yield an analog error signal. The error signal is amplified by a factor A to bring the error within the fullscale range of Q3 in amplifier A2, converted to digital format in quantizer Q3, and scaled back down by a factor of A in a digital divider 26 to compensate for the amplification of A2. The resulting digital error signal at the output of divider 26 is combined with the digital predicted signal from predictor 18 in the output summing junction 20 to produce the final converter output.
While the circuit of FIG. 2 avoids the use of sample-and-hold circuits with their attendant dynamic range limitations, and also uses only a single quantizer as opposed to the two quantizers in the circuit of FIG. 1, it does have significant disadvantages. If the input is overdriven with respect to the full scale capability of the DAC, a large error is produced in the DAC output. This error includes high frequency components that are beyond the designed input bandwidths of the predictor. Outside these bandwidths large amplification takes place and builds up in a positive feedback loop, eventually resulting in an output oscillation between the positive and negative voltage supply bus levels. A similar instability can result from high frequency signals that enter the circuit from other sources, such as extreme quantizing errors and noise spikes. In addition to a capability for detecting an unstable operating condition, the system must have a reset capability once the instability has been detected. The time required for reset may be beyond the permissible limits of the overall system into which the ADC is connected, such as certain radar systems.
ADCs that incorporate both a predictor circuit and a sample-and-hold function are disclosed in U.S. Pat. No. 4,792,787 to Speiser et al., in the Harris article mentioned above, and in McKnight et al., "Developments in the Techniques for Enhancing the Dynamic Range of Analog to Digital Converters", PROC. ICASSP, 1988. These circuits perform a sample-and-hold on an analog error signal, rather than on the input analog signal directly, and thereby avoid much of the dynamic range limitations associated with FIG. 1. However, they can still become unstable if the input is overdriven or slews too fast.